The DRAM is an important memory device and, due to its versatility and low fabrication cost, has been widely used in such fields as computer, communication, home appliance, etc. As electronic technologies advance and as higher demands are continuously being made on the storage capability and functionality of the DRAM, one necessary approach is to improve the integration level of the DRAM. However, an available to a capacitor used in the DRAM has to be reduced as the integration level of the DRAM is improved.
However, as the area of the memory device is reduced continuously, a too large leakage current has become a significant factor that affects the quality or performance of the DRAM.
An existing method for fabricating a DRAM was disclosed by Chinese Patent No. 03178608. As seen in FIG. 1A, an n− buried layer 101 is formed by implanting phosphorus ions into a P-type silicon substrate 100 with a dosage of 1×1013 ions/cm3 and an energy of 1.25 MeV. A P-type well 102 is formed by implanting boron ions into the P-type silicon substrate 100 twice. A gate oxide layer 103 is formed on the P-type silicon substrate 100, and a polysilicon layer 104 is formed on the gate oxide layer 103. A metal silicide layer 105 is formed on the polysilicon layer 104, and a silicon nitride layer 107 is formed on the metal silicide layer 105, thus forming a gate structure 106 composed of the gate oxide layer 103, the polysilicon layer 104, the metal silicide layer 105 and the silicon nitride layer 107.
As seen in FIG. 1B, boron ions are implanted into the P-type well 102 by an ion implantation method so as to regulate a threshold voltage of the P-type well 102. With the gate structure 106 as a mask, a first lightly-doped drain 108 is formed by implanting phosphorus ions into the P-type well 102 at both sides of the gate structure 106 with a dosage of 1×1013 ions/cm3 and an energy of 15 KeV.
As seen in FIG. 1C, a photoresist layer 110 is formed on the P-type silicon substrate 100, and the gate structure 106 is covered by the photoresist layer 110. An opening 112 is formed at one side of the gate structure by exposing and developing the photoresist layer 110. With the photoresist layer 110 as a mask, boron fluoride is also implanted into the P-type well 102 corresponding to the opening 112 so as to prevent the source and drain from being broken down subsequently.
As seen in FIG. 1D, a first arsenic bit line contact window 116 is formed by implanting arsenic ions into the P-type well 102 corresponding to the opening 112, with the photoresist layer 110 as a mask.
As seen in FIG. 1E, the photoresist layer 110 is stripped to form a spacer 114 at both sides of the gate structure 106, and with the gate structure 106 as a mask, a second lightly-doped drain 118 is formed by implanting phosphorus ions into the P-type well 102 with a dosage of 2×1013 ions/cm3 and an energy of 20 KeV. Here, an area including the first and second lightly-doped drains 108 and 118 can be defined as a source 120, and an area including the first and second lightly-doped drains 108 and 118 and the first bit line contact window 116 can be defined as a drain 122.
As seen in FIG. 1F, an insulation oxide layer 124 is formed on the P-type silicon substrate 100, and the insulation oxide layer 124 at the drain 122 is etched until the P-type silicon substrate 100 is exposed, thus forming a contact hole 126. Then a second arsenic bit line contact window 128 is formed by implanting arsenic ions into the P-type well 102 at the drain 122.
As seen in FIG. 1G, the contact hole 126 is filled with tungsten to connect the drain 122 and a bit line 130, and a capacitor (not shown) is fabricated at the drain 120, thus forming a DRAM.
As can been seen from the above DRAM fabrication in the prior art, there are three N-type ion implantations of phosphor ions at the bit line contact window and there is a large gradient of dosages and energies among them. Hence implantation depths of phosphorus ions can varied considerably, resulting in a relatively large PN junction leakage current. Thus the DRAM has a high power consumption when it is used for a low power consumption product.